A communication amount is increasing in data communication between information processing devices, and there is a limit in enlarging the number of wiring together with a bit width in parallel data transmission. In order to correspond to an increase in communication amount, there is a case where a serializer/deserializer (SerDes) is mounted on each device to carry out data communication between the devices by serial data transmission.
FIG. 15 is a diagram illustrating a configuration example of a serializer/deserializer. A serializer/deserializer 601 includes a control circuit 602, an oscillation circuit (PLL) 603, a transmission system (TX) circuit, a reception system (RX) circuit, and so on. The transmission system circuit receives parallel data inside a device on which the serializer/deserializer 601 is mounted and converts into serial data by performing parallel-serial conversion by a multiplexer (MUX) 604, thereafter shaping a voltage waveform by a feed forward equalizer (FFE) 605 and outputting to outside the device via a driver 606.
The reception system circuit receives serial data from outside the device via an equalizer 607 and reproduces data and a clock signal by a decision feedback equalizer (DFE) 608 and a clock data recovery (CDR) 609. The reception system circuit converts this data into parallel data by performing serial-parallel conversion by a demultiplexer (DMUX) 610, and outputs to a processor or the like inside the device.
FIG. 16A is a diagram illustrating a configuration example of a conventional demultiplexer used for a serializer/deserializer. FIG. 16A illustrates the demultiplexer which converts serial data inputted to the demultiplexer into 4-bit parallel data, as an example. Note that in the present specification <“signal name” X> or <“signal name” x> is a logically inverting signal (complementary signal) of “signal name” signal.
In FIG. 16A, a 1:2 conversion circuit 701 converts inputted serial data DATA into 2-bit parallel data, by using frequency divided clock signals CLK2, CLK2x outputted from a frequency divider 702. The frequency divided clock signals CLK2, CLK2x are clock signals obtained by frequency-dividing (½ frequency dividing) inputted clock signals CLK, CLKX into twofold cycles.
The 1:2 conversion circuit 701 includes four latch circuits 711, 712, 713, 714 connected as illustrated in FIG. 16B. In each of the latch circuits 711 to 714, a value of an input D is transmitted to an output Q when the inputted clock signal is at a high level, the value of the input D is latched at falling (at a time of transition from the high level to a low level) of the clock signal, and the output Q is held when the clock signal is at the low level. The 1:2 conversion circuit illustrated in FIG. 16B converts serial data DATA which transits in synchronization with the clock signal CLK into 2-bit parallel data D0, D1 which transits in synchronization with the frequency divided clock signal CLK2 which is the twofold cycle of the clock signal CLK, as illustrated in FIG. 16C.
The 1:2 conversion circuits 703, 704 convert data of each bit in 2-bit parallel data having been converted by the 1:2 conversion circuit 701 as serial data into 2-bit parallel data by using the frequency divided clock signals outputted from the frequency divider 705. The frequency divided clock signals outputted from the frequency divider 705 are clock signals obtained by ½ frequency-dividing frequency divided clock signals CLK2, CLK2x. Configurations of the 1:2 conversion circuits 703, 704 are similar to that of the 1:2 conversion circuit 701.
As described above, the conventional demultiplexer ½ frequency-divides the input clock signal, and latches the data by the latch circuit in the 1:2 conversion circuit at falling (or rising) of the frequency divided clock signal, whereby to convert the serial data into 2-bit parallel data. Further, by repeating frequency division of the clock signal and division of the data (conversion from the serial data into the 2-bit parallel data), the conventional demultiplexer generates 2n-bit parallel data.
FIG. 17A is a diagram illustrating a configuration example of a conventional multiplexer used for a serializer/deserializer. FIG. 17A illustrates the multiplexer which converts 4-bit parallel data inputted to the multiplexer into serial data, as an example.
In FIG. 17A, a 2:1 conversion circuit 801 converts 2-bit parallel data DIN0, DIN1 in inputted 4-bit parallel data into 1-bit serial data, by using a frequency divided clock signal outputted from a frequency divider 803. A 2:1 conversion circuit 802 converts 2-bit parallel data DIN2, DIN3 in the inputted 4-bit parallel data into 1-bit serial data, by using the frequency divided clock signal outputted from the frequency divider 803. The frequency divided clock signal outputted from the frequency divider 803 is a clock signal obtained by frequency-dividing (½ frequency-dividing) clock signals CLK, CLKX inputted to a 2:1 conversion circuit 804 in a later stage into a twofold cycle.
The 2:1 conversion circuit 804 converts a group of 1-bit serial data each which has been converted by the 2:1 conversion circuits 801, 802, that is, 2-bit parallel data, into 1-bit serial data DOUT, by using the inputted clock signals CLK, CLKX. The 2:1 conversion circuit 804 includes four latch circuits 811, 812, 814, 815 and two pass gates (switches) 813, 816 which are connected as illustrated in FIG. 17B.
In each of the latch circuits 811, 812, 814, 815, a value of an input D is transmitted to an output Q when the inputted clock signal is at a high level, and the value of the input D is latched at falling (at a time of transition from the high level to a low level) of the clock signal, and the output Q is held when the clock signal is at the low level. Each of the pass gates (switches) 813, 816 comes to be ON (continuity state) when an inputted control signal is at a high level, and comes to be OFF (non-continuity state) when the control signal is at a low level. The 2:1 conversion circuit illustrated in FIG. 17B converts 2-bit parallel data D0, D1 into serial data OUT whose data rate is twofold in relation to the parallel data D0, D1, as illustrated in FIG. 17C.
As described above, the conventional multiplexer latches the data of each bit of the inputted parallel data by the latch circuit at falling (or rising) of the clock signal and thereafter outputs via the pass gate which is synchronized with the clock signal, in the 2:1 conversion circuit. For 2n-bit parallel data, the conventional multiplexer repeats n-stage data conversion (conversion from 2-bit parallel data to 1-bit serial data) by using a clock signal having been frequency-divided.
In order to realize a high-speed operation in the conventional demultiplexer or multiplexer, a timing accuracy between the clock signal including the frequency divided clock signal and the data signal is important, and highly-accurate timing control is required. Further, when a bit width of data is large, the number of data conversion becomes large due to repetition of data conversion by the conversion circuit, each circuit repeating inversion of an inner potential with a latching action, so that a power consumption becomes large.
There is suggested a semiconductor integrated circuit that includes a first counter which generates a first signal of a cycle obtained by multiplying a clock signal from a rising edge of the clock signal, a second counter which generates a second signal of a cycle obtained by multiplying the clock signal from a falling edge of the clock signal, and an exclusive logical sum operation circuit which generates a clock signal by performing an exclusive logical sum operation of the first signal and the second signal, to output to a circuit unit (see Patent Document 1, for example). This semiconductor integrated circuit is intended to suppress variation of delay time of the clock signal to each circuit, by providing the plurality of exclusive logical sum operation circuits between terminals of a first line to which the first signal is transmitted and a second line to which the second signal is transmitted, and the circuit unit.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2010-41156